In a processor supporting virtual memory, the virtual address provided by the CPU has to be translated to a physical address. This is typically accomplished by a Memory management unit (MMU). The MMU typically uses a μTLB (micro-translation look-aside buffer) as a cache of the address translation entries stored in the MMU. Such address translation entries are typically organized based upon memory pages. Every virtual address requested by CPU needs to be translated to the physical address by the μTLB/MMU for memory access. This is typically performed on page boundaries. If the series of program fetches cross a boundary into the next page, then the next address translation entry is needed for virtual to physical address translation. If this next address translation entry is not in the μTLB, it must be requested from the MMU. This translation data fetch may take tens to hundreds of cycles depending on the page translation and page table walk latency in the MMU.